The repair of thin film wiring using TSM (Top Surface Metal) repair lines is well known. In the conventional repair process, a defective electrical wiring net, used to connect components on a multichip carrier, is disconnected from its internal wiring through specialized delete locations located at the "C4" (Controlled-Collapsed-Chip-Connection) joining, pads. The net is reconstructed with equivalent electrical performance by connecting the X-Y grid of the repair lines on the top surface to the required C4 pads, matching the timing of the original net.
The reconstruction of the net is normally accomplished by joining the segments of the surface repair lines with individual gold ribbons bonded to the TSM repair lines through a lasersonic bonding methodology. The gold ribbons interconnect specific X and Y repair line segments to rebuild the net topography. FIG. 1 illustrates a portion of a conventional multi-chip module (MCM) before repair. In FIG. 1, C4 connection 10 is connected to net 12 at via 14. X repair line 16 and Y repair lines 18, 20 are part of the top layer. Y repair lines 18, 20 are connected by Y repair line subway 22 using vias 24, 26. Vias 14, 25, 26 connect to down levels. C4 connection 10 has a repair elbow 28 and a bond site 30.
FIG. 2 is a plan view of the portion of the device shown in FIG. 1 after the conventional repair process. (FIG. 3 is a cross-sectional view taken along the line 3--3 of FIG. 2.) When a defect is found in net 12, it is completely disconnected from the circuit using external delete 32 between C4 connection 10 and via 14. This process is repeated at every other C4 connection location for net 12. To replace this deleted net, a portion of X repair line 16 and Y repair lines 18, 20 must be used. Conventionally, X repair line 16 and Y repair lines 18, 20 are cut using deletes. Then, C4 connection 10 is connected to X repair line 16 using gold ribbon 34, and X repair line 16 is connected to Y repair line 20 using gold ribbon 36.
In a multi-layer thin film structure, most of the top-to-top wiring nets, which connect chip C4 through the thin film layers structure, can be repaired via top surface repair lines. For top-to-bottom nets, which connect C4 to peripheral I/O, however, there is no established repair methodology. Presently, all I/O repairs are made on a case by case basis, and partial repair and sacrificial repair methods have been employed for some special and simple I/O defects situations. A direct I/O plate-up repair method is a general repair approach, however, the current TF designs do not contain the needed repair features connecting capture pads (C/P) to C4 pads. The I/O repairability is also a slow and elaborate task, and does not have the manufacturability required for a production line.
A multilayer thin film module is typically processed on the surface of a MLC (Multi-Level Ceramic) carrier. After the structure is built, a full after-thin-film test is performed to confirm the integrity of the thin film structure. At this stage, if a defect is found to be associated with a top-to-bottom I/O net, then the part is in general considered unrepairable and will be rejected. There are some special situations when an I/O defect can be repaired by employing the concept and technique of graphical assisted partial repair. In general, however, there is no systematically established method to repair top-to-bottom I/O nets. The reason for the unrepairability in I/O nets is simply the inaccessibility of the top-to-bottom portion of I/O nets in the thin film on ceramic carrier design structure.
In a typical TF wiring design, about 30% of the capture pads (C/P) and 50% of the C4 (chip joining sites) are not used. Currently, these unused pads are only filled in by design and have no functionality.
In view of the shortcomings of the prior art, a reliable TF processing alternative is needed to improve the top-to-bottom repair process of thin film products.